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Altera_Forum
Honored Contributor
Honored ContributorData Transfer from FPGA-to-HPS
Hi, I am very new to the Altera FPGA suite (and FPGAs in general), and was looking to get some advice on how to transfer data from the FPGA to the HPS. I've done fair amount of research, but I ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- First off thanks! Now going off what you said I think the F2H bridge is the best option for me so I don't have to worry about the cache coherency issues of the SDRAM bridge. Speed I don't believe should be an issue since I only need 80Mbitps transfer speeds, and I saw in another forum post that the bridge has 133 MHz frequency and I know it can support 128-bit width so that would give 2.12Gigabytes per second? In the case that I use the F2H bridge to setup DDR3 writes how would that look? I have found plenty of examples of H2F and the H2F lw, but none of the F2H except for the Altera one, which I can't seem to get to work on my DE0-Nano-SoC since it was written for the Cyclone V dev board. Thanks again for all your help! --- Quote End --- Re: bandwidth, 2 GB/s would be only achievable with burst transfers. When writing one word at a time, it may be less (possibly much less). Not sure. As in my first example, instantiate an altera_hps and an altera_avalon_mm_bridge. Connect bridge.m0 -> hps.f2h_axi_slave. Export bridge.s0. Now you have access to signals: mm_bridge_0_s0_waitrequest mm_bridge_0_s0_address mm_bridge_0_s0_writedata mm_bridge_0_s0_write When you have data to send, essentially, put 1 into 'writedata', put your data into 'write', and put the physical address of RAM where you want to write into 'address', and wait for 'waitrequest' to go down. See https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/mnl_avalon_spec.pdf (it's rather complicated).
