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Honored Contributor
7 years agoThere are basically two options.
First, you could hook up the FPGA to HPS bridge and carve out some DDR3 RAM to be used for storage purposes. The FPGA to HPS bridge has the master on the FPGA side and the slave in the HPS side. So, the FPGA side is the one issuing write requests, those requests have to go into some virtual memory space, and it might as well be RAM (unless it is a HPS-side peripheral.) You could write into RAM through the FPGA->SDRAM bridge, but that is not guaranteed to maintain cache coherency (so, as I understand, HPS-side memory reads may result in old data, even after the transfer, if it happens to be in the cache.) FPGA->HPS is slower than FPGA->SDRAM, but should be plenty fast enough for your task. Alternately, you could go the other way around. In Qsys/Platform Designer, instantiate an altera_hps, an altera_avalon_onchip_memory2, and an altera_avalon_mm_bridge. Hook them up like so: altera_hps.h2f_axi_master -> altera_avalon_onchip_memory2.s1 altera_avalon_mm_bridge.m0 -> altera_avalon_onchip_memory2.s1 Export altera_avalon_mm_bridge.s0. Now you have some on-chip RAM (the amount configurable through altera_avalon_onchip_memory2's properties) that you can write on FPGA side through the pins you just exported and read on HPS side starting at the address 0xC0000000. The downside is that you don't have a whole lot of RAM to work with (your entire chip has something like 300 kbytes worth of M10Ks) so you need to be frugal. P.S. I'm basically learning this as I go along myself, so take this with a grain of salt.