Data synchronization issue

Thanks for the reply rbugalho... But I don't understand what gets wrong if I used the dcfifo in this case...

Also I used the signaltap with reference clock set at clka... I saw that the counter is perfectly at clkb (for example i generated 15 continues valids on clkb domain after certain period) but on the other side i.e. at clka domain I see sometimes 15 and sometime 14 and sometime 16 valids.... I also counted the valids using a counter on clka domain... In other words I am pretty sure that logic is correct but I am not sure about the synchronization or clock jitter... I also checked that there is no negative slack between clock domains.

Please help... I am running out of time