Honored ContributorI just working around with a design of wireless device with EP4CE40F29C7N.
But what is the aggregate single peak data rate of this ? I can only find the data rate info about the GX device, but seems not the E device.
Honored ContributorData Rate? How are you calculating this?
In the GX devices, you are probably looking at the high speed transceivers (SERDES IO's) That are rated at up to 3.125 Gbps. The E variant do not have SERDES transceivers so that specification doesn't apply. You can still have it work for wireless device, but the wireless data rate has nothing to do with the SERDES specification. In an E device, you have CMOS/TTL/LVDS etc io, which all have maximum switching rates associated with them but can be paralleled together to achieve very high data rates. It's just on a parallel bus vs a very high speed single pin. The maximum clock frequency of the device in an FPGA is highly depended on what you need it to do per clock cycle, and how full the device is. So although they may state a clock tree performance of 300-500 MHz, depending on speed grade, in general you can only get very limited logic to run at that rate. Pete
