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Sorry ,
maybe I was a little too fast.
Is your picture a signaltap or a simulation output ? Can you zoom in so that it is possible to see all value ?
Kind regards
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Hi,
you mentioned that RdBuf is a "reg", but as far as I know you can't use "assign" for reg.
assign RdBuf = ( CpuDataVld &HRCW_over_flag )? CpuDataOut : 8'hzz ;
CpuData is a Toplevel port ? What is connected to this port ?
assign CpuData = ( CpuDataVld &HRCW_over_flag )? {8'h00,CpuDataOut} : 16'hzzzz ;
According to your assignment CpuData is only during CpuDataVld "1" = CpuDataOut. With
CpuDataVld "0" you switch back to "z". Maybe somebody is driving the port ?
Can you zoom in your traces, in orde to see what values are caaptured ?
Kind regards
GPK
Honored Contributor
