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Altera_Forum's avatar
Altera_Forum
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17 years ago

Data corrupted, any problem with VHDL codes

HI everyone. I just have a quick question to ask. When we use the LOOP in VHDL, is there any chances that the number of times the LOOP is repeated affects the data, say, in the following pie...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

YEAHHHH, EXCELLENT, I've just tried to put a CLKINT (which make the clock line global) and the problem disappears. I have had some problems which were solved by using a CLKINT before, but didn't know why it helped. Now turns out it's all about the clock skew problem.

Yeah, it is a correlator that I'm designing, I tried 2 methods, the other was to use a series of Shift register and Multipliers, but no way it's fit in the chip I was given. The MAC method involves so many problems, it's a nightmare.

Could you think of any other methods?

J.