Data corrupted, any problem with VHDL codes

Ahhh. You didn't use the Global clock! In that case I definitely think you have a clock skew problem, basicaly the data from one latch is bing clocked out in advance of the data to the next latch being clocked in - it's a common problem with large shift registers (I used Actel devices nearly 20 years ago and experienced same) but using a Global clock rather than normal routing should cure it as the skew over the global clock will be much much less than if you've used local routing for the clock.