Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorData corrupted, any problem with VHDL codes
HI everyone. I just have a quick question to ask. When we use the LOOP in VHDL, is there any chances that the number of times the LOOP is repeated affects the data, say, in the following pie...
Altera_ForumHonored Contributor
Honored ContributorActually, I used an Actel FPGA (which I don't like but company does) for this design, not Altera. Is there any chances the way the the logic elements and the net were placed and routed inside the chip corrupted the data?
