Data between gated clk's

Gated clocks are undesirable in FPGAs for several reasons, however I understand why you are doing this. As you discovered, they often create hold time violations. If you must use them, then turning on 'Optimize Hold Timing' to All Paths should fix the problem as you discovered, however it does this by increasing the routing delay of the data path to the destination register(s). This is better for timing analysis than adding a similar delay to the source clock (by manually adding a gate). You can verify that the timing is met by looking at the path in TimeQuest before and after making the setting to All Paths. You will see the increased routing delay to the destination register.