Daisy Chain JTAG & Serial configuration device connections in Cyclone - II FPGA

Hi Magalingam,

Since your JTAG chain includes lots of devices, its important to include buffers/drivers on the signals. I'd recommend a buffer at the JTAG header with ESD protection, and then buffer/fanout of the TCK/TMS signals. Take a look at this example (which has 7 devices in the JTAG chain);

http://www.ovro.caltech.edu/~dwh/carma_board/

http://www.ovro.caltech.edu/~dwh/carma_board/gda06rb004_carma_v0.87_dec03.pdf

p7 of the schematic has a block diagram showing you the JTAG chain, p44, p77, p78 has the of the buffering. Note how the nCEO of each of the FPGAs turns off a red LED, i.e., the red LEDs are on when the FPGAs are powered by not configured. The LEDs go off once the FPGAs are configured. This makes it easy to see when the FPGAs are configured.

Do these FPGAs all operate independently? If not, why not just configure them from a common source, eg., a MAX II CPLD plus a flash device containing the configuration image for all 5 FPGAs?

http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf

You do not really need the AS headers for the SPI EEPROMs. You can use .jic programming via JTAG.

Cheers,

Dave