Cylone II FPGA Clock input

Your specification suggests an AC coupled clock source and possibly signal overshoot. The FPGA maximum ratings must be unconditionally kept to avoid device damage. Also the level and maximum rise-time specifications of the respective I/O standard should be considered to achieve reliable operation.

As said, a usual 3.3V clock oscillator can be directly connected to the FPGA clock input, for traces longer than 1", a source side termination resistor may be recommended. If you have a non-standard clock source, a level conversion is most likely necessary.

P.S.: You may experience difficulties to measure the actual clock waveform with an usual passive oscilloscope probe and particularly it's unsuitable standard ground connection.