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ENava's avatar
ENava
Icon for New Contributor rankNew Contributor
2 years ago

CycloneIV-E external ADC parallel interface timings

Hi all. I'm interfacing a CycloneIV-E to a AD9266 ADC and I'm struggling trying to close timings. FPGA design has one 100MHz pll clock; the adc is clocked with a divide-by-two register (=50MHz); da...
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SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
1 year ago

From the timing report, seem this issue probably related to CDC. Have you tried to constraint the CDC between the 2 different clocks?

This might be the reason why you are having a large skew. Multicycle path or synchronizer is the way to handle this.