CycloneIII internal logic driving PLL

Have a look at the PLL User Guide for info on dynamic phase shifting:

http://www.altera.com/literature/ug/ug_altpll.pdf (http://www.altera.com/literature/ug/ug_altpll.pdf)

I couldn't find any specific examples on using this feature, so I would recommend putting together a simple simulation so you can determine how exactly it operates.

You would still need to provide an external clock to the PLL in order to use it with the dynamic phase shifting feature, though I am not sure how this would help you. Your original post mentions data / strobe signals, but not the availability of the original clock.

Another option maybe to over-sample the incoming datastream, depending upon the frequency. You would then use the over-sampled clock to drive your internal logic. I have seen this done when decoding Manchester Phase Encoded data. The key is to have a low frequency stream to start with, so the over-sampling frequency is manageable by the core logic.

Stephen