CycloneIII internal logic driving PLL

Hi Terry,

What you want to do is not directly supported by the CycloneIII PLLs - I don't think any other families support this either. The likely reason is to minimize jitter - using the dedicated clock input pins provide a direct low-jitter path to the input of the PLL. Feeding the input of the PLL from the core fabric would increase this, likely compromising the PLL performance.

Here's a possible work around: send the XOR-ed signal out of the device and then back in on an adjacent clock pin, which would then feed a PLL. Not ideal, but it should get you out of trouble.

Good luck.

Stephen