cyclone4 JTAG issue

dear alex,

Is there a specific power up sequence we need to follow for FPGA's?? Presently we are using dual output(3V3 and 1V2)TI-70145 regulator configured to power up VCCINT and then VCCIO of FPGA.(schematic is attached). And 2V5 is powered up from TLV1117 which powers up at start up.

Also i need to mention here that similar power supply section has already been used in a single FPGA board and the DESIGN was stable.

The only difference in this design is that we are using a common 2V5 regulator for all the VCCA's of three on board FPGA's. And also i am observing that the FPGA going faulty(U2) is located farthest from the 2V5 regulator(though we have put decaps near the FPGA pins).

Also as u pointed out one doubt, the difference between U2 FPGA and other FPGA's on board is that some of it I/O pins are interfaced to a RANDOM LOGIC GENERATOR whose OUTPUT VARIES AT EVERY INSTANT. AND WE HAVE KEPT THOSE PINS UNASSIGNED IN OUR DESIGN SO FAR.

KINDLY CONFIRM THAT WHETHER THIS CAN CREATE SUCH JTAG ISSUES AFTER SOME TIME??