I'd be more concerned about the design's power supplies and general signal integrity. How are the rails for the FPGA(s) being generated? How good are they? Poorly designed power solutions, that present unwanted noise/transitions to the FPGA, can manifest themselves in strange ways.
What is different about U2 as compared to the others? Are some of it's I/O pins being subjected to unwanted noise/transients that might be damaging the FPGA? Signals that come from off-board, that are not conditioned locally, can frequently cause issues.
If 155mm was the issue I'd expect you to see JTAG integrity issues straight away and not after a period of time. You also suggest you have another board which works well?
What are you hosting the JTAG chain with - a USB-Blaster, or something else?
JTAG trace lengths can be an issue - the drivers are relatively weak. However, it's unlikely to result in device damage.
Cheers,
Alex