Cyclone10LP SEU CRC error implementation

K**bleep**ij,

I already clock the cyclone10lp_crcblock but the output signal regout is stucked to 0 (I check it with signaltap).

As you don't see the attachment, here is the IP instantation and the process to clock out the data :

//----- Instantiation and configuration -------------------------------------------------------

uut_cyclone10lp_crcblock : cyclone10lp_crcblock
generic map
(
oscillator_divider => 8 ,
lpm_type => "cyclone10lp_crcblock"

)
Port map
(
clk => s_clk_crcblock ,
shiftnld => s_shiftnld ,
ldsrc => s_ldsrc ,
crcerror => s_crcerror ,
regout => s_regout
);

s_shiftnld <= '0';
s_ldsrc <= '0';

s_clk_crcblock <= i_clk when s_output_crc='1' else '0';

o_regout <= s_regout;

o_error_pin <= s_crcerror;

//----- Process to output data -------------------------------------------------------

pro_get_crc32: process(i_clk)
begin

if i_rst = '0' then

sv_cnt <= (others=>'0');
sv_crc32 <= (others=>'0');
s_output_crc <= '0';

elsif rising_edge(i_clk) then

-- Wait 10 s @ 60MHz then output register : 600000000
if unsigned(sv_cnt) = 600000000 then
s_output_crc <= '1';
sv_cnt <= std_logic_vector(unsigned(sv_cnt) + 1);

-- Stop after 32 clocks 600000032
elsif unsigned(sv_cnt) = 600000032 then
s_output_crc <= '0';
sv_cnt <= std_logic_vector(unsigned(sv_cnt) + 1);

-- Stop counter 33 clocks 600000033
elsif unsigned(sv_cnt) = 600000033 then

-- Count after reset
else
sv_cnt <= std_logic_vector(unsigned(sv_cnt) + 1);
end if;

if s_output_crc = '1' then

sv_crc32 <= sv_crc32(sv_crc32'length-2 downto 0) & s_regout;

end if;

end if;
end process;

Regards,

Gorka BIROT