Cyclone VE starts config from N25Q then fails midstream

Are you confident the DE0-CV development platform is capable of booting at 100MHz?

The DE0-CV ships with a standard EPCS64 whose max operating frequency is 20MHz - 40MHz if fast read is enabled, something none of the reference designs use. Add to that the board's embedded USB-Blaster CPLD, which also connects up to the same serial flash, and you already have a less than ideal topology for the higher speed operation you're after.

In any final solution you may capture you're unlikely to be hanging anything else of the serial FLASH, allowing you to realise a layout that will operate at 100MHz. This I have done, using the same Numonyx/Micron device you've mentioned. Terasic have captured a design that offers flexibility - at a cost - the cost being a board that (probably) won't support the higher speed configuration.

So, I expect the FPGA is seeing errors in the configuration stream. I assume it will boot at a lower speed...?

Cheers,

Alex