Cyclone V

Hello.

It is necessary to accept a serial code with a speed of 768 Mbps and to transform it to a parallel 8-bit code with a frequency of 96 MHz.

Proceeding from an objective, what IP-core you will recommend to use?

There were attempts of implementation of this project on Custom PHY Tranciever. There were following questions:

1) How there is a synchronization at reception of serial signal? (How I can organize this synchronization?)

2) When using Custom PHY Tranciever is it possible to use only levels 1.5 PCML?

3) Do you have any recommendations for realization of this problem?

I use next equipment:

- Cyclone V GX Starter Kit

The used software:

- Quartus II 13.1 (64-bit)