Cyclone V XCVR configuration for SATA I application.

Dear Sir,

I made several tries and I found a configuration that allows detecting the COMWAKE signal.

The configuration that works for me is:

cfast_sata_rx_p Receiver Signal Detection Unit Enable/Disable On

cfast_sata_rx_p Receiver Signal Detection Voltage Threshold 7

cfast_sata_rx_p Receiver Cycle Count Before Signal Detect Block Declares Loss Of Signal 0

cfast_sata_rx_p Receiver Cycle Count Before Signal Detect Block Declares Presence Of Signal 2

cfast_sata_tx_p Transceiver Analog Settings Protocol SATA1_M

cfast_sata_rx_p Transceiver Analog Settings Protocol SATA1_M

Now I have another problem with the signal detect.

After the COMWAKE signal, the SATA protocol requires that the FPGA receives 54.6us of ALIGN primitive at 6 Gbps, 54.6us of ALIGN primitive at 3 Gbps and 54.6us of ALIGN primitive at 1.5 Gbps.

My signal detect behavior is like this:

I have a stable signal detect for the first 109.2us (54.6us of ALIGN primitive at 6 Gbps and 54.6us of ALIGN primitive at 3 Gbps), but a not stable signal detect for the last 54.6us.

The questions are:

1) Does the SIGNAL DETECT not stable means that the Native PHY is not working properly?

2) Is the SIGNAL DETECT not stable because I set the "Receiver Cycle Count Before Signal Detect Block Declares Loss Of Signal" to 0?