Cyclone V XCVR configuration for SATA I application.

Hi,

As I understand it, you are running SATA Gen1m with CV XCVR and observe some issue with the RX signal detect during the OOB init sequence. If I understand it correctly, you have configured the signal detect settings following the Altera XCVR PHY IP Core user guide -> "Enable rx_std_signaldetect port" section for Cyclone V Transceiver Native PHY IP Core.

The following are the assignments from user guide:

• set_instance_assignment -name XCVR_RX_SD_ENABLE ON

• set_instance_assignment -name XCVR_RX_SD_THRESHOLD 7

• set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_OP55V

• set_instance_assignment -name XCVR_RX_SD_OFF 1

• set_instance_assignment -name XCVR_RX_SD_ON 2

Mind cross check with your QSF assignments to see if there is any discrepancy?

If the assignment is the same with user guide already, you can try with the following set of settings to see if it helps:

• set_instance_assignment -name XCVR_RX_SD_ENABLE ON

• set_instance_assignment -name XCVR_RX_SD_THRESHOLD 5

• set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_OP65V

• set_instance_assignment -name XCVR_RX_SD_OFF 3

• set_instance_assignment -name XCVR_RX_SD_ON 5

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin