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New Contributor

5 years ago

[Cyclone V SoC] Trouble implementing FPGA-to-HPS Bridges Design Example (Intel Design Example)

Hello all, First of all, I am a novice when it comes to soc development. I was trying to implement Intel's FPGA-to-HPS Bridges Design Example (https://www.intel.com/content/www/us/en/programmable/su...

AnilErinch_A_Intel

Frequent Contributor

5 years ago

Please try any other example like hello world or FFT as given in the link below, so that we can be sure that

any edits like SDRAM settings edit or script changes are not causing this issue.

https://software.intel.com/content/www/us/en/develop/articles/terasic-de10-nano-get-started-guide.html#explore-fft

Thanks and Regards

Anil

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[Cyclone V SoC] Trouble implementing FPGA-to-HPS Bridges Design Example (Intel Design Example)

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