[Cyclone V SoC] Trouble implementing FPGA-to-HPS Bridges Design Example (Intel Design Example)

Hi

Please try any other example like hello world or FFT as given in the link below, so that we can be sure that

any edits like SDRAM settings edit or script changes are not causing this issue.

https://software.intel.com/content/www/us/en/develop/articles/terasic-de10-nano-get-started-guide.html#explore-fft

Thanks and Regards

Anil