Cyclone V SoC Preloader will not run bare metal app

Hello all,

I've been working on this problem for several days now. I've read every website/pdf I can find (e.g. these forums, rocketboards, altera pdfs, etc, etc, etc, etc) regarding bare metal applications on Cyclone V SoC and I still can't get this to work. I've gotten pretty far but I've basically run out of steam. I usually never post on forums unless I've tried every possible thing I can think of and have totally run out of ideas and places to search. I think I must just be missing something very simple.

Here's what I've done so far (targetting DE10-Nano board):

1) Created basic HPS design with UART and SDMMC peripherals enabled and DDR3 settings configured same as golden reference design that was provided with the board

2) Built hardware design to .SOF without error and converted SOF to RBF so that it can be loaded by pre-loader

3) Using the 'hps_isw_handoff' I created the spl_bsp with bsp-editor and configured to boot from SDMMC

4) Compiled preloader using 'make' which generated preloader-mkpimage.bin without error

5) Ran alt-boot-disk-util to update pre-loader image on special partition of SD card

6) Created SD/MMC example C project in SoC EDS application (from https://www.altera.com/content/dam/altera-www/global/en_us/others/support/examples/soc/altera-socfpga-hardwarelib-sdmmc-cv-gnu.tar.gz)

7) Compiled example C project to .AXF with no errors using baremetal GCC arm-altera-eabi- toolchain

8) Copied AXF file to SD card FAT partition and inserted SD card into board

9) Powered on board

Pre-loader uboot output is as follows:

U-Boot SPL 2013.01.01 (Sep 04 2017 - 20:01:43)
BOARD : Altera SOCFPGA Cyclone V Board
CLOCK: EOSC1 clock 25000 KHz
CLOCK: EOSC2 clock 25000 KHz
CLOCK: F2S_SDR_REF clock 0 KHz
CLOCK: F2S_PER_REF clock 0 KHz
CLOCK: MPU clock 800 MHz
CLOCK: DDR clock 400 MHz
CLOCK: UART clock 100000 KHz
CLOCK: MMC clock 50000 KHz
CLOCK: QSPI clock 3125 KHz
RESET: COLD
INFO : Watchdog enabled
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION PASSED
SDRAM: 1024 MiB
ALTERA DWMMC: 0
U-Boot 2017.03-rc2 (Mar 30 2017 - 19:07:16 -0700)
CPU:   Altera SoCFPGA Platform
FPGA:  Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
BOOT:  SD/MMC Internal Transceiver (3.0V)
       Watchdog enabled
I2C:   timeout in enabling I2C adapter
timeout in enabling I2C adapter
ready
DRAM:  1 GiB
MMC:   dwmmc0@ff704000: 0
timeout in enabling I2C adapter
timeout in enabling I2C adapter
In:    serial
Out:   serial
Err:   serial
Model: Terasic DE10-Nano
Net:   No ethernet found.
Hit any key to stop autoboot:  0
=> run fpga_cfg
reading de10-nano.rbf
1952756 bytes read in 192 ms (9.7 MiB/s)
=> load mmc 0:1 0x01000000 sdmmc_example.axf
reading sdmmc_example.axf
669244 bytes read in 73 ms (8.7 MiB/s)
=> bootelf
CACHE: Misaligned operation at range 
CACHE: Misaligned operation at range 
CACHE: Misaligned operation at range 
CACHE: Misaligned operation at range 
CACHE: Misaligned operation at range 
CACHE: Misaligned operation at range # # Starting application at 0x00100040 ...
INFO: System Initialization.INFO: Setting up Global Timer.INFO: Setting up SDMMC.RESULT: Some failures detected.

As you can see the pre-loader loads the FPGA design file. The configuration DONE light turns on so I know configuration is successful.

However, the example application fails. Clearly there are some cache issues but I have no idea what they mean or why they are happening. But then the example application starts and just fails with no indication as to why. I inserted some printfs into the example code and it fails at the call to alt_sdmmc_card_identify().

I'm not sure if the 0x01000000 address that I'm loading to makes sense. The only reason that I'm using it is because that's the address that the 'bootelf' command tries to load from.

It's obvious that the SD card peripheral is working since the pre-loader can read from it. I also tried changing the u-boot environment variables and writing them back to the SD card and that worked as well. So SD card read/write operation seems OK.

It's also obvious that the DDR is working because the pre-loader can clearly write the ELF file to the DDR at address 0x01000000 and the HPS can obviously read from it since the application does in fact run (just not successfully).

Can someone please help me figure this out?

Regards

P.S. I'm not interested in using the debugger to load the application. I need the fpga design and application to be loaded off of the SD card as I've shown. So please don't reply with "use the debugger and make a debug script" or similar. I need the board to boot and just start running without cables attached.

UPDATE: I've also tried the GPIO example from the altera website (https://www.altera.com/content/dam/altera-www/global/en_us/others/support/examples/soc/altera-socfpga-hardwarelib-gpio-cv-gnu.tar.gz) and doesn't even successfully print the first printf statement. Instead it just prints a bunch of garbage:

=> load mmc 0:1 0x01000000 gpio_example.axf
reading gpio_example.axf
610864 bytes read in 64 ms (9.1 MiB/s)
=> bootelf
CACHE: Misaligned operation at range 
CACHE: Misaligned operation at range 
CACHE: Misaligned operation at range 
CACHE: Misaligned operation at range 
CACHE: Misaligned operation at range 
CACHE: Misaligned operation at range # # Starting application at 0x00100040 ...-ÊÊêJåÍѵ%¹¥Ñ¥±¥é?½¹¹J9=éJ¹¥ÑA%=j½Õ±¹J9=éÑÑ¥¹ÕÁA%=¥¹ÑÉÉÕÁ?J9=??ÕÁ:A%=½Éb?J9=é?ÕÁA%=½ÉAÕÍ¡     ÕÑ?¹¹J9=?¥ÍÑ?¥¹ÑÉÉÕÁ?¢¹±É¹J9=é?ÍÍ"AM}A  }UMI}ÁéBAM0?    ±¥¹*¹J9=??ÍÍ!AM}A       }UMI}ÅéB5b5E5??±±?¡Ñ¹J9=??ÍÍBAM}A       }UMI}ÉêBAM"???±±b?J9=??ÍÍ!AM}A }UMI}ÍÒB5b)E5ÒÕ?½¹á¥Ñ¢µ½¹