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Altera_Forum's avatar
Altera_Forum
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10 years ago

Cyclone V SOC Maximum Speed

Hi, I'm trying to build SPI master with SCK speed as high as possible. For some reason, my target SPI SCK is 166MHz. I'm using DE0-NANO-SOC board running Linux socfpga 3.13. The software contro...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

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Hi,

Is there any specification about what is the highest internal bus speed and highest I/O speed for this device? I can't find it in the datasheet. Anyway to further push up the speed? Right now my SPI core is connedted to the DQ physical pin in bank 3A with 3.3LVTTL standard.

1. Can the speed be increased if I change the physical IO to other pins / standard?

Thank you in advance.

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Hi,

I believe there is no spec on the max IO data rate available in the device datasheet currently. To further increase the data rate, you can try to play around with different IO standards, current strength and slew rate to see if can further boost the data rate.