Forum Discussion
Altera_Forum
Honored Contributor
11 years agoHi Maor,
Indeed, bank 4A and 3B share their VCCPD. That means you can't have a 3.3V IO in bank 4A (VCCIO4A=3.3V and VCCPD=3.3V) and at the same time an LVDS IO in bank 3B (VCCIO3B=2.5V and VCCPD=2.5V). VCCPD=2.5V is a requirement for implementing LVDS and using Rd OCT as well. Altera statements are not always very clear in documents (like "VCCPD must be greater or equal to VCCIO of the same bank") but you'll find additional information in: C5 Handbook: p5.10, p5.18 and p5.43 altera knowledge database: http://www.altera.com/support/kdb/solutions/rd01312014_45.html (http://www.altera.com/support/kdb/solutions/rd01312014_45.html) You have to move either your 3.3V IO or LVDS IO to another bank which does not share the VCCPD. That's the only safe way. PS: To be true, some years ago, I did such a mistake in a previous design (Stx IV): I powered the VCCPD pins of a 2.5V VCCIO bank with 3.0V instead of 2.5V. I told Quartus, these were LVDS inputs with Rd OCT... Though the VCCPD pin were expecting 2.5V, there were no consequence (maybe because the relevant pins were used as LVDS AC-coupled inputs). A worse situation would have been to power VCCIO with a 3.0V as well. In that case, It would have been quite unlikely to have working LVDS IOs even by cheating the fitter with false IO standard assignments :oops: (according to Stx IV docs, LVDS is not supported if VCCIO is 3.0V) Nevertheless, if you can avoid such a situation before your PCB is done, it would be much less risky !...