Cyclone V SE Power management

Hi,

The power estimator is able to display static power. For the HPS, you can reduce the freq during compilation (it will change the divider of PLL). Unfortunately, I don't see any power management system inside the HPS (for example, to automatically change PLL divider). There is a software example that will put the MPU to IDLE mode though:

https://www.altera.com/support/support-resources/design-examples.html#socdesignexamples

(search for "Power Optimization" under SoC design examples

Another way you can reduce power is to power down the FPGA when unused. Of course this means the regulator control will have to be done by HPS. If this is relevant to you, I've seen an example project that does that.