Forum Discussion
Altera_Forum
Honored Contributor
10 years ago --- Quote Start --- Hi, Apologies for not responding to my own thread! It has taken a long time to get my head around this problem. Out of interest which particular variant of the Cyclone V SoC are you trying to enable partial reconfiguration on (it does make a difference!) Alex --- Quote End --- Okay, that is an absolutely fascinating model. I've not seen those before-- but it definitely would be a nice feature to have in the fabric. This is essentially adding a boundary-scan feature to every LUT, though, which makes me wonder about its feasibility and resource usage in current designs. Looks good though. But what this doesn't solve is the fact that the FPGA Manager itself is able to accomplish partial reconfiguration and the driver isn't written for it... were you able to work on this, or was everything done using a custom AXI module? Thanks! Fascinating read.