Cyclone V QSPI flash controller slaves

Only 1 test I know: on link upper and it in your second questions line. It introduce us to HPS-C-side of work and give to find/see in alt_qspi.c a functions "alt_qspi_chip_select_config_get()" and "*_set()", which operates with bits 13:10 of main (first) register "cfg" of QSPI-controller (see page 15-22 of cv_5v4.pdf, field "percslines") to set chip enables qspi_n_ss_out[3:0] in any combination. 2 and more bits in 1 simultaneously is error -- think I.

However, this functions is not called in test, bits 13:10 of cfg is==0 -- apparently, chip on board is selected hardly.

Near is described register "delay" (offset C) with delays between assert/deassert any chip select bits.

P.S. I'm sorry, not see "Quad SPI Porting", only "Quad SPI", № 6.

"the following QSPU"... :)

This example № 8 may expand set of compatible devices, exclude onboard :)

You may add our device to these princip ?