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jrrguzman
Occasional Contributor
Occasional ContributorCyclone V PLL Normal compensation not working as it should
Hi, I'm trying to meet IO timing with a Cyclone V based design. The design uses a clock (135 MHz) connected to a dedicated clock PAD with direct connection to the PLLs. After setting up the PLL into...
jrrguzmanOccasional Contributor
Occasional ContributorHi,
Could anyone from Intel/Altera give me any feedback about this topic? Are my assumptions right or am I missing something regarding the compensation modes for the Cyclone V PLL?
The issue is as follows:
I am using a PLL with normal compensation. From my understanding this compensation should account for the clock routing delay from the PLL to the registers, making the skew between the PLL input clock and the clock arriving at the register almost 0. What I see when I implement the design is that I have a skew of several nanoseconds, no matter what I do. This becomes specially bad when I try to drive the IO registers and meet timing.
Thanks in advance.
