Cyclone V PLL Normal compensation not working as it should

Hi,

After running timing analysis and checking any IO path, I see that the PLL compensation does not cover the whole delay introduced by the clock network by far.

If I check the Cyclone V device handbook Volumen 1 I get this (p91, s4-33):

An internal clock in normal compensation mode is phase-aligned to the input clock pin. The external clock output pin has a phase delay relative to the clock input pin if connected in this mode. The Intel Quartus Prime TimeQuest Timing Analyzer reports any phase difference between the two. In normal compensation mode, the delay introduced by the GCLK or RCLK network is fully compensated.

So from that statement and the image describing normal mode compensation provided by Intel/Altera within the same document I should see almost 0 skew between the clock PLL input fref and any register driven by the PLL output.

Maybe I am confusing or misunderstanding how the compensation works. That's why I'm posting this on the forum.

Cheers