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Aiswarya's avatar
Aiswarya
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4 years ago

Cyclone V PCIe Avalon-ST interface GEN1 x1 test-bench IP - Handling of multiple MSI requests

I am using Cyclone V PCIe Gen1x1 IP core in my project. To verify this design, Altera PCIe Root port BFM is used as the test-bench. While verifying the MSI requests generated from the DUT, it has bee...
skbeh's avatar
skbeh
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4 years ago

When the Hard IP asserts interrupt, it just means the HIP has created the interrupt message and sent out. It does not mean the message is really out of the TX pin. It also does not mean the host has serviced the interrupt.
When the host side receives the interrupt, it needs to run the interrupt service routine to service the interrupt.
If requesting interrupts too fast, it might get extra interrupts. Next interrupt should only be requested after the previous interrupt being serviced.