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is there any way to input a clock in a single dedicated pin and distribute that by global clock to all the corner fractional plls
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The fact that Quartus will not let you probably means no.
I had a similar question regarding providing Stratix IV+V transceivers on two sides of an FPGA a common reference clock, and the only acceptable solution to the fitter was to use separate REFCLK pins; one on each side of the FPGA. This indicates it is necessary to use an external clock buffer.
This is not exactly what you want to hear if your board is already built, but if you are performing an analysis of what is possible before you design your board, then I think you will need to have at least two reference clocks, i.e., one to each side of the FPGA, and from there you might be able to lock the fractional PLLs.
Cheers,
Dave
Honored Contributor
