Cyclone V LVDS deserializer bitrate

Hello Carlos.

As about your last question -

"By changing the individual I/O delays, do you mean to change them using the IOBUF configurable input delay?"

Well, yes, from the assignment editor you can manually set different I/O delay, and even you can dynamically adjust delays in modern devices.

Also from ECO mode, you could adjust I/O delays after compilation, which is very useful if your compile time is significant.

As about the measurement of LVDS signals - in case you haven't an option of measurement using oscilloscope you can try to use the internal SignalTap logic analyzer. The idea is somewhat like that (I will try to explain but not sure it will be clear) - you create a signal tap system together with In system source and probes or System Console or other for controlling the I/O delays dynamically. After that, you need to start acquisition of your signal (of course for ADC for example it's known test pattern), and what you need is to find iteration where your data is closer to be 50% correct to 50% incorrect. That will be a position where you are in the metastable state, you need to iteratively move from that point to receive your data more and more correctly. So because you know the amounts of delay step and know the most close to metastable position of your data, you can estimate edges of your LVDS signals.

Hope that helps.

Best regards,

Ivan