Cyclone V LVDS deserializer bitrate

Hello Ivan

From the tool we did not get any warning regarding I/O assignments or anything. Plus, we are using a dedicated bank for all the LVDS signals and only LVDS signals, there is no single-ended signal in that bank. Using Quartus Prime v16.1 we did not get any message regarding possible crosstalk or SSN effects.

Thank you so much for all the advices. For the skew between the different LVDS pairs we took into consideration a couple of rules to design the trace length. Basically, the maximum skew is below 50ps with a maximum mismatch of 30ps between the positive and negative lines. These two references we took them from [1]

I do not find it so straightforward to check if the edges of all the LVDS signals are aligned, first because we do not have a couple of differential active probes to measure with the oscilloscope, and with Signaltap we should sample at a frequency at least equal than those 560MHz. Do you have an idea of how could we check this?

By changing the individual I/O delays, do you mean to change them using the IOBUF configurable input delay?

Best regards,

Carlos

[1] - JOHNSON, Howard; GRAHAM, Martin. High-speed signal propagation: advanced black magic. 2003