Cyclone V LVDS deserializer bitrate

Hi Spieler.

There are lots of possible reasons for mistake.

First of all ideally you need to find out if there are PCB bugs and also you should check I/O assignment analysis for warnings.

Also SSN should be taken into account. If you will type actual toggle rate for your I/O pins you will receive more actual analysis results

from I/O assignment analysis.

Also of course I recommend to verify your timing constraints.

Then, maybe on one or several pairs you have some timing shift, ideally you need to look using oscilloscope if all edges from your LVDS lines are aligned, but you can also try to find out that using signal tap. After that you can change individual I/O delays to correct timing.

Best regards,

Ivan