Cyclone V LVDS & DDR3 on same bank

Just got this reply from Altera Tec Support saying that I can do this on a Cyclove V:

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[Q1]: Assuming that the LVDS input buffers are powered from VCCPD = 2.5V, can I use the LVDS differential inputs if VCCIO is set to 1.5V fro DDR3?

[A1]: Referring to the Cyclone V device handbook, it says,

“If VCCIO is set to 2.5 V or lower (eg. 1.2, 1.25, 1.35, 1.5, 1.8V), VCCPD must be powered up to 2.5 V. This applies for all the banks containing the VCCPD and VCCIO pins.”

Meaning that if an I/O bank uses a 2.5-V VCCPD (for LVDS), the I/O bank can use different VCCIO voltages provided they are 1.2, 1.25, 1.35, 1.5, 1.8, or 2.5 V.” Thus, for your setup, VCCPD = 2.5V and VCCIO = 1.5V is allowable by Quartus II.

It should [not] be a problem if the design had completed the Quartus compilation without errors message. Quartus will sure give you an error message if the setup is not allowable.

[Q2]: Can I use RD OCT? If not, can I do it with external RD?

[A2]: You are not allowed to use RD OCT, as stated in the device handbook, you can only use RD OCT when you set both the VCCIO and VCCPD to 2.5 V. For your case, VCCPD = 2.5V and VCCIO = 1.5V, you could use external RD. Please refer to the Figure 5–7 which showing the setup of External On-Board Termination.

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supernode:

"The only strange thing is that Quartus will not bring up an error for this configuration, even when using differential termination on that pin pair."

Yes, that's strange. I get the same result with Quartus; implying that termination can be used...