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Altera_Forum's avatar
Altera_Forum
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13 years ago

Cyclone V LVDS & DDR3 on same bank

Hello, I am planning to use a Cyclone V 5CGTFD7D5F31 with the following requirements; - 32 bit DDR3 interface Top and Bottom (64 bit total) - 68 LVDS input p...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Sorry, it's just the information that LVDS inputs are not supported on VCCIO 1.5V banks and a link to the VCCIO / IO Standard matrix.

Well thats for an Arria chip; I suggest you upen a separate service request for your particular device - maybe that has a different behavior or you get a more detailed description on that.

Our LVDS clock input is now placed on a 2.5V bank and when Quartus 12.0 is release, it hopefully brings the needed bugfix for the engineering samples. I will not investigate more time on that topic.