Cyclone V IO Timing Issue

Hi all,

I am currently facing some issue with Cyclone V IO Timing. I have found that in CV device, it fail both input and output timing at 200 MHz clock frequency.

Attached is the sample project to simulate this issue. This is a very simple project where the input bus is feed to the output bus through one sets of register. Tuning the setup and hold time cannot eliminate the timing violation. The only way to eliminate the timing violation is to reduce the clock frequency.

However I have tried the same project on a CIV device of same package and it don't have this issue. Since CV is built on newer technology, I am expecting that CV device should have better or equivalent timing performance.

FYI the IO assignment is random by using back annotate assignment. The Quartus version is 14.0 and the device is 5CGXFC7D7F31C8N.

Please help on this issue.

Thanks.