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jkhoo's avatar
jkhoo
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Cyclone V GX starter Kit : XCVR_LOOPBACK_TEST clocking from REFCLK_p0 to PLL Reconfig inside xcvr ip

Hi Intel team, In the C5G_HSMC_XCVR_LOOPBACK_TEST project, clock generator si5338 CLK1A (U20.Pin18) with default frequency of 125Mhz is connected to REFCLK_p0. And REFCLK_p0 is routed to hsmc_xc...
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ZiYing_Intel's avatar
ZiYing_Intel
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi,

Currently there is no a probable reason that why is the PLL reconfiguration reference clock freq set to 100Mhz when the project top entity is getting default freq of 125Mz from si5338 because it might be caused by many factors.

Best regards,

Zi Ying