Forum Discussion
Mikexx
Occasional Contributor
Occasional ContributorCyclone V: Dynamic phase shift
I am implementing this using the PLL Intel FPGA Megafunction (ALTERA_PLL) Is this the best IP to use where I wish to adjust phase relationships? I can't find any documentation to suggest the phase ...
FvM
Super Contributor
Super ContributorHi,
phase step resolution is 45°*Fout/Fvco.
If the PLL configuration tool is free to vary vco frequency, the phase step setting will be considered. But often vco frequency is already fixed by output frequency parameters, in so far the respective statement in device handbook can be misleading.
Regards
Frank
MikexxOccasional Contributor
Occasional ContributorThanks for the reply.
Although the input and output frequencies are both 50MHz, I can see under "Advanced Parameters" the "PLL Output VCO Frequency" is "300.0 MHz".
So I assume from that there should be 48 steps.
