Cyclone V clock pin driver output impedance

ADC clock input is usually capacitive, the pin capacitance should be specified in datasheet.

Don't know what's the required clock input level. If you need full TTL/CMOS voltage swing, e.g. 2.5 or 3.3Vpp, source side termination as mentioned in post# 3 can achieve almost perfect signal shape. If termination is needed at all depends mainly on the transmission line length between FPGA and ADC. Some ADCs have differential clock inputs that can be best driven by LVDS IO standard with 100 ohm load side termination.