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I have a similar question to this. I'm designing a DDR3 interface in a Cyclone V 5CEBA5 F484 device. I'm using bank 4A as the interface because it has 48 pins of which I'm using 40. There are no PLL clock out pins in this bank so I've allocated 2 CLKIN pins, CLK2p and CLK2n for my DDR_CLK and DDR_CLK_N outputs. The fitter hasn't 'complained' so my question is are these clock outputs being treated as ordinary I/O whose delay will change each time it's run through Quartus?
Thanks,
Clive
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Think I've found an answer. The External Memory Interface Handbook Vol 2 states in section 1.1.2 "you should generate the CK and CK# signals using the DDR registers in the IOE to match with the DQS signal ". I'm using the DDR3 SDRAM Controller with UniPHY MegaCore so presumably this will do it all for me :)?
Could someone please confirm this for me?
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