Cyclone V clock output pins

The PLL clock output pins have dedicated, fast routing, so that the delay to these pins is minimised or, perhaps more importantly, known.

Using ordinary I/O will result in Quartus using up ordinary routing resources, whose delay will change each time you run your design through Quartus. So, depending on your board design, and what this output clock is used for, you may end up with a working board one minute and a non-working board the next courtesy of a new FPGA build, even though you may not have changed anything to do with the output clock in your FPGA design.

Cheers,

Alex