Cyclone V: A PLL with multiple clocks and independently adjusting phase of a clock

The only way I can think that the same clock would get affected by more than one selection of cntsel[] would be if some of the cntsel bits are tied to a static value by mistake. The only exception is when all of the cntsel bits are high, then all of the clocks will be phase shifted at the same time. Maybe you can put the cntsel bits in signal tap and verify they are toggling as expected?