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TonyK's avatar
TonyK
Icon for New Contributor rankNew Contributor
3 years ago

Cyclone V 2.5V LVPECL vs LVDS inputs

When feeding an AC coupled LVPECL differential signal into a Cyclone V FPGA, the Cyclone V datasheet appears to indicate that DC bias and OCT 100 ohm differential termination is not available when As...
Core Logic
EthanLi's avatar
EthanLi
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Hi,

This is Ethan from Intel AE team.

LVPECL inputs are limited to CLK input pins.

Do you use the transceiver pin or GPIO pin? If it is a GPIO pin, there is no internal AC/DC coupling.

If it is a transceiver pin, you can turn on the OCT option in the assignment.

For the assignment , you can refer to the KDB below.

https://www.intel.com/content/www/us/en/support/programmable/articles/000083679.html

You need to specify LVDS in Quartus since if you specify LVPECL the fitter will error if Rd is turned on. The reason why we don’t support Rd with LVPECL is the larger common mode range – our Rd doesn’t meet its tolerance specs at the expanded LVPECL range compared to LVDS. The termination does not meet all the specs at the expanded LVPECL range to LVDS.

So please make sure LVPECL vocm and vod meets our LVDS receiver’s specs.

Thanks,

Ethan