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Altera_Forum
Honored Contributor
Honored ContributorCyclone V + ALTLVDS + Multi-channel ADC
Dear all, I am trying to fit a design in a Cyclone V FPGA (E series, A7, FBGA 484 pins). The FPGA receives 16 LVDS channels at 875 Mbps each. The data comes from a LTM9011-14 ADC from Linear Tec...
Altera_ForumHonored Contributor
Honored ContributorThe parameters in the initial post makes sense if Giancarlo wants to use 2-lane 14-bit mode at 125 MSPS.
