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Honored Contributor
Honored ContributorCyclone V - Megafunction "ALTIOBUF" Error
hello, i have some problems using QuartusII megafuction "ALTIOBUF". <I'm using Cyclone V(Cyclone V GX Starter Kit) and Quartus 13.1> I create a new megafunction(ALTIOBUF-select 'As an output ...
Altera_ForumHonored Contributor
Honored ContributorHi,
generally speaking you need to instantiate an IP in your top level file and not set it as the top level file. In VHDL the keyword is components instantiation and I am sure it named similar in Verilog HDL.
