Cyclone V - Megafunction "ALTIOBUF" Error

Thanks for your reply.

i make the output buffer 'IOBUF_OUT.v' using MegaWizard Plug-in Manager.

Top Level(TEST.v) code and IOBUF_OUT.v code are as follows :

module TEST(

out_datain,

out_io_config_clk,

out_io_config_clkena,

out_io_config_datain,

out_io_config_update,

out_oe,

out_dataout

);

input out_datain;

input out_io_config_clk;

input out_io_config_clkena;

input out_io_config_datain;

input out_io_config_update;

input out_oe;

output out_dataout;

IOBUF_OUT u2 (

.datain(out_datain),

.io_config_clk(out_io_config_clk),

.io_config_clkena(out_io_config_clkena),

.io_config_datain(out_io_config_datain),

.io_config_update(out_io_config_update),

.oe(out_oe),

.dataout(out_dataout));

endmodule

//synthesis_resources = cyclonev_delay_chain 2 cyclonev_io_config 1 cyclonev_io_obuf 1

//synopsys translate_off

`timescale 1 ps / 1 ps

//synopsys translate_on

module IOBUF_OUT_iobuf_out_ll61

(

datain,

dataout,

io_config_clk,

io_config_clkena,

io_config_datain,

io_config_update,

oe) ;

input [0:0] datain;

output [0:0] dataout;

input io_config_clk;

input [0:0] io_config_clkena;

input io_config_datain;

input io_config_update;

input [0:0] oe;

`ifndef ALTERA_RESERVED_QIS

// synopsys translate_off

`endif

tri0 io_config_clk;

tri0 [0:0] io_config_clkena;

tri0 io_config_datain;

tri0 io_config_update;

tri1 [0:0] oe;

`ifndef ALTERA_RESERVED_QIS

// synopsys translate_on

`endif

wire wire_sd1_dataout;

wire wire_sd2_dataout;

wire [4:0] wire_ioconfiga_outputenabledelaysetting;

wire [4:0] wire_ioconfiga_outputregdelaysetting;

wire [0:0] wire_obufa_i;

wire [0:0] wire_obufa_o;

wire [0:0] wire_obufa_oe;

wire [0:0] oe_w;

cyclonev_delay_chain sd1

(

.datain(datain[0]),

.dataout(wire_sd1_dataout),

.delayctrlin({wire_ioconfiga_outputregdelaysetting[4:0]}));

cyclonev_delay_chain sd2

(

.datain((~ oe_w[0])),

.dataout(wire_sd2_dataout),

.delayctrlin({wire_ioconfiga_outputenabledelaysetting[4:0]}));

cyclonev_io_config ioconfiga_0

(

.clk(io_config_clk),

.datain(io_config_datain),

.dataout(),

.dutycycledelaysettings(),

.ena(io_config_clkena),

.outputenabledelaysetting(wire_ioconfiga_outputenabledelaysetting[4:0]),

.outputfinedelaysetting1(),

.outputfinedelaysetting2(),

.outputhalfratebypass(),

.outputonlydelaysetting2(),

.outputonlyfinedelaysetting2(),

.outputregdelaysetting(wire_ioconfiga_outputregdelaysetting[4:0]),

.padtoinputregisterdelaysetting(),

.padtoinputregisterfinedelaysetting(),

.readfifomode(),

.readfiforeadclockselect(),

.update(io_config_update)

// synopsys translate_off

// synopsys translate_on

);

cyclonev_io_obuf obufa_0

(

.i(wire_obufa_i[0:0]),

.o(wire_obufa_o[0:0]),

.obar(),

.oe(wire_obufa_oe[0:0])

`ifndef FORMAL_VERIFICATION

// synopsys translate_off

`endif

,

.dynamicterminationcontrol(1'b0),

.parallelterminationcontrol({16{1'b0}}),

.seriesterminationcontrol({16{1'b0}})

`ifndef FORMAL_VERIFICATION

// synopsys translate_on

`endif

// synopsys translate_off

,

.devoe(1'b1)

// synopsys translate_on

);

defparam

obufa_0.bus_hold = "false",

obufa_0.open_drain_output = "false",

obufa_0.lpm_type = "cyclonev_io_obuf";

assign

wire_obufa_i = {wire_sd1_dataout},

wire_obufa_oe = {(~ wire_sd2_dataout)};

assign

dataout = wire_obufa_o,

oe_w = oe;

endmodule //IOBUF_OUT_iobuf_out_ll61

//VALID FILE

// synopsys translate_off

`timescale 1 ps / 1 ps

// synopsys translate_on

module IOBUF_OUT (

datain,

io_config_clk,

io_config_clkena,

io_config_datain,

io_config_update,

oe,

dataout);

input [0:0] datain;

input io_config_clk;

input [0:0] io_config_clkena;

input io_config_datain;

input io_config_update;

input [0:0] oe;

output [0:0] dataout;

wire [0:0] sub_wire0;

wire [0:0] dataout = sub_wire0[0:0];

IOBUF_OUT_iobuf_out_ll61 IOBUF_OUT_iobuf_out_ll61_component (

.io_config_clk (io_config_clk),

.io_config_clkena (io_config_clkena),

.oe (oe),

.datain (datain),

.io_config_datain (io_config_datain),

.io_config_update (io_config_update),

.dataout (sub_wire0));

endmodule