Cyclone V - LVDS input on a bank with Vccpd=2.5V and Vccio=1.8V
Hello,
I'd like to have a confirmation of what I found on the Cyclone V Device Handbook regarding mixed voltage standards on a single bank.
In my design I have multiple I/Os @ 1.8V and LVDS inputs on the same bank. Quartus doesn't issue any errors and the project compiles and fits successfully. I've done this because on the Handbook (Table 5-9: Cyclone V I/O Standards Voltage Levels) it's specified that LVDS inputs are only dependent to Vccpd, which is equal to 2.5V on my bank. There's also a note which says: "Input buffers for the SSTL, HSTL, Differential SSTL, Differential HSTL, LVDS, RSDS, Mini-LVDS, LVPECL, HSUL, and Differential HSUL are powered by VCCPD".
Can someone confirm that?
Thank you
Hi Zak,
There is no issue to use mixed voltage standards on a single bank. As long as that particular I/O bank supported your I/O standard (Vccpd=2.5V and Vccio=1.8V)
Regards,
Matt