New Contributor
Regular ContributorHi,
These are the interfaces, you need to refer to the Cyclone V HPS TRM, f2h interrupts:
https://www.intel.com/content/www/us/en/docs/programmable/683126/21-2/interrupts-38262.html
DMA controller interface:
Alternatively, you may want to look at an example design below from Robertofem:
New ContributorHi,
thanks, I have already seen these resources before.
In the first site there is no information about using f2h interrupts directly with the DMA Controller. Of course I could use an interrupt kernel driver writing the DMA control register but that's not what I am looking for.
The second link you provided also doesn't explain how to connect the DMA Peripheral Requests (f2h_dma_reqX) to the DMA Controller QSYS. It also doesn't say how the DMA controller in the HPS is related to the QSYS component.
The third link provides source code (fpga_dmac_api.c) I have been already using (ie. the CONTROL register I mentioned in the first post). But it also doesn't relate to the interrupts or to triggering of the DMA from the FPGA side.
The only way I can think of right now is accessing the control_port_slave (Avalon MM Slave) of the DMA Controller QSYS component directly from the fabric but it would mean sharing the physical address of the allocated buffer from HPS first, which doesn't seem like a valid approach to me.
What's the proper way to accomplish this?
